## 1 Bit Full Adder Design using Logisim Bangla Tutorial

###### 1 bit Full Adder design using Logisim:

This is tutorial is in Bangla language.

## Digital Logic: Binary to Gray Code Converter

Before starting with this read Digital Logic: Designing Decimal to 4 bit Gray Code Converter if you are unfamiliar.

##### Binary, Decimal and Gray Code Table:

Here I am representing gray code bits with A, Decimal values with D and Binary bits with B.

 Binary Decimal Gray Code B3 B2 B1 B0 D A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 2 0 0 1 1 0 0 1 1 3 0 0 1 0 0 1 0 0 4 0 1 1 0 0 1 0 1 5 0 1 1 1 0 1 1 0 6 0 1 0 1 0 1 1 1 7 0 1 0 0 1 0 0 0 8 1 1 0 0 1 0 0 1 9 1 1 0 1 1 0 1 0 10 1 1 1 1 1 0 1 1 11 1 1 1 0 1 1 0 0 12 1 0 1 0 1 1 0 1 13 1 0 1 1 1 1 1 0 14 1 0 0 1 1 1 1 1 15 1 0 0 0
##### Binary to Gray Code Converter:

This same technique can be applied to make gray to binary converter. There will be 4 input bits, which represent binary and 4 output bits which represent equivalent gray code.

Since we are creating binary to gray code converter so, we need to find expressions for each gray code output in terms of input binary bits.

So, there will be four output bits $A_3, A_2, A_1, A_0$. For these output bits the input will be different combinations of $B_3, B_2, B_1, B_0$ based on minimized expression.

## A3:

Minimized expression from the above k map,
$A_3 = B_3$

## A2:

Minimized expression from the above k map,
$A_2 = B_3 \overline{B_2} + B_2 \overline{B_3}$

But, the expression of XOR Gate is (Let, A and B be the inputs),
$A.\overline{B} + B.\overline{A} = A \oplus B$
[Note: This is not related to this problem but, only showing how XOR can be made from And, Or, Not gates]

Similarly,it can be shown that,
$B_3 \overline{B_2} + B_2 \overline{B_3} = B_2 \oplus B_3$

If XOR gate is not available then the former expression can be used with and, or and not gates to design the gray code converter.

## A1:

Minimized expression from the above k map,
$A_1 = B_1 \overline{B_2} + B_2 \overline{B_1}$

Similarly,it can be shown that,
$B_1 \overline{B_2} + B_2 \overline{B_1} = B_1 \oplus B_2$

## A0:

Minimized expression from the above k map,
$A_0 = B_0 \overline{B_1} + B_1 \overline{B_0}$

Similarly,it can be shown that,
$B_0 \overline{B_1} + B_1 \overline{B_0} = B_0 \oplus B_1$

## Digital Logic: Designing Decimal to 4 bit Gray Code Converter

##### Gray Code:

Difference of gray code from binary is that, for each group only one bit changes when going from one number to the next. In case of binary it can be seen from the table that multiple bit may change when going from one number to next.

##### How to Create Gray Code Sequence:

There are multiple shortcut technique to write gray code. This is the technique I follow,

0
1


Next step, Add 0’s before both of them,

0 | 0
0 | 1


Next Mirror ( Write the values bottom to top instead of top to bottom ) all bits except for Left Most bit and Add 1’s in the place left most bit,

0 | 0
0 | 1
------> Mirror
1 | 1
1 | 0


Continuing this process again of adding 0’s before all numbers and Mirroring all bits except left most bit, then adding 1’s in place of left most bit,

0 | 0 0
0 | 0 1
0 | 1 1
0 | 1 0
-------> Mirror
1 | 1 0
1 | 1 1
1 | 0 1
1 | 0 0


Now following same procedure for 4 bits,

0 | 0 0 0
0 | 0 0 1
0 | 0 1 1
0 | 0 1 0
0 | 1 1 0
0 | 1 1 1
0 | 1 0 1
0 | 1 0 0
--------> Mirror
1 | 1 0 0
1 | 1 0 1
1 | 1 1 1
1 | 1 1 0
1 | 0 1 0
1 | 0 1 1
1 | 0 0 1
1 | 0 0 0


finally 4 bit gray code representing Decimal 0 to 15,

0 0 0 0
0 0 0 1
0 0 1 1
0 0 1 0
0 1 1 0
0 1 1 1
0 1 0 1
0 1 0 0
1 1 0 0
1 1 0 1
1 1 1 1
1 1 1 0
1 0 1 0
1 0 1 1
1 0 0 1
1 0 0 0


Now just start from the top with 0 and increment it by 1. That will be the decimal equivalent of the gray code.

##### Binary, Decimal and Gray Code Table:

Here I am representing gray code bits with A, Decimal values with D and Binary bits with B.

 Binary Decimal Gray Code B3 B2 B1 B0 D A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 2 0 0 1 1 0 0 1 1 3 0 0 1 0 0 1 0 0 4 0 1 1 0 0 1 0 1 5 0 1 1 1 0 1 1 0 6 0 1 0 1 0 1 1 1 7 0 1 0 0 1 0 0 0 8 1 1 0 0 1 0 0 1 9 1 1 0 1 1 0 1 0 10 1 1 1 1 1 0 1 1 11 1 1 1 0 1 1 0 0 12 1 0 1 0 1 1 0 1 13 1 0 1 1 1 1 1 0 14 1 0 0 1 1 1 1 1 15 1 0 0 0

##### Making Decimal to Gray Converter:

Since this is Decimal to Gray Code converter, the Binary part of the table could be omitted.

$A_3 = D_8 + D_9 + D_{10} + D_{11} + D_{12} + D_{13} + D_{14} + D_{15} \\ A_2 = D_4 + D_5 + D_6 + D_7 + D_8 + D_9 + D_{10} + D_{11} \\ A_1 = D_2 + D_3 + D_{4} + D_{5} + D_{10} + D_{11} + D_{12} + D_{13} \\ A_0 = D_1 + D_2 + D_5 + D_6 + D_9 + D_{10} + D_{13} + D_{14} \\$

Let,

$X_1 = D_4 + D_5 \\ X_2 = D_8 + D_9 \\ X_3 = D_{10} + D_{11} \\ X_4 = D_{12} + D_{13} \\ X_5 = X_2 + X_3 \\$

From the above expression,

$A_3 = X_2 + X_3 + X_4 + D_{14} + D_{15} \\ .... = X_5 + X_4 + D_{14} + D_{15} \\ \\ A_2 = X_1 + D_6 + D_7 + X_2 + X_3 \\ .... = X_1 + D_6 + D_7 + X_5 \\ \\ A_1 = D_2 + D_3 + X_1 + X_3 + X_4 \\ \\ A_0 = D_1 + D_2 + D_5 + D_6 + D_9 + D_{10} + D_{13} + D_{14} \\ \\$

##### Inputs and Outputs:

For the circuit there will be inputs each representing a decimal number. The number of outputs will be 4 from $A_3 \text{ to } A_0$ where, $A_0 \text{ is the LSB and } A_3 \text{ is the MSB}$.

##### How to test if its working:

Just press each buttons in the left one at a time then check to see if the values given match the value in table. The values are read bottom to top, equivalent to reading values from table left to right.

##### Circuit Diagram:

Download the file named 4 bit decimal to gray code converter circuit diagram from my Github.

## Digital Logic Designing an Arbitrary Counter

##### Design an arbitrary counter that counts or follows in this sequence:
0, 2, 4, 5, 7, 0, 2, 4........

It is pretty clear from the question that counter counts in,

0 -> 2 -> 4 -> 5 -> 7 -> 0 -> 2 -> 4 -> …….

It goes from 0 to 2 then 4 this way. After reaching 7 it goes back to beginning of the sequence and repeats the sequence.

#### Arbitrary Counter State Diagram:

Since nothing is said about what will happen if it had to transition from 1, 3 and 6. So I can choose on my discretion what the next state will be from those unused states.

#### Arbitrary Counter State Table:

When simplifying input equations, unused states can be used as don’t care conditions or it may also be assigned specific next states. Here unused or unreachable states are 1, 3, 6 so these states can have any assigned next state of designers choice.

The reason or advantage of using don’t care is easier state diagram, smaller state table, easier k-map equations as well as less connections in the logic diagram etc.

There is also a good reason to use specific next states from unreachable states instead of using don’t care conditions. Such as during operation due to outside interference the may reach an unused state and break the intended sequence. Also it may keep circulating in unused states and never come back to original sequence.

Here I have only shown K Map and Logic Diagram using don’t care term for transition of unused states and using J-K Flip Flops.

#### Excitation Table:

The excitation table below are for J-K, D, S-R, T latches. For making arbitrary counter with these latches fill the state table from the excitation table.

J-K:

$\begin{tabular}{ | l | l | l | p{1cm} |} \hline Q & Q(next) & J & K \\ \hline 0 & 0 & 0 & x \\ \hline 0 & 1 & 1 & x \\ \hline 1 & 0 & x & 1 \\ \hline 1 & 1 & x & 0 \\ \hline \end{tabular}$

D:

For D latch the next state is the output.

$\begin{tabular}{ | l | l | l | p{1cm} |} \hline Q & Q(next) & D \\ \hline 0 & 0 & 0 \\ \hline 0 & 1 & 1 \\ \hline 1 & 0 & 0 \\ \hline 1 & 1 & 1 \\ \hline \end{tabular}$

S-R:

$\begin{tabular}{ | l | l | l | p{1cm} |} \hline Q & Q(next) & S & R \\ \hline 0 & 0 & 0 & x \\ \hline 0 & 1 & 1 & 0 \\ \hline 1 & 0 & 0 & 1 \\ \hline 1 & 1 & x & 0 \\ \hline \end{tabular}$

T:

$\begin{tabular}{ | l | l | l | p{1cm} |} \hline Q & Q(next) & T \\ \hline 0 & 0 & 0 \\ \hline 0 & 1 & 1 \\ \hline 1 & 0 & 1 \\ \hline 1 & 1 & 0 \\ \hline \end{tabular}$

#### How to complete the state table:

First thing is to complete the present state. Since we have only 0, 2, 4, 5, 7 to count, fill in their binary representation. No need to show the rest or like I mentioned above.

Next, Fill up the next state based on present state. Like shown in the state diagram above from 0 it next counts to 2, then 4, then 5 etc.

So next state of 0 is 2. Which in binary is 000 to 010. Similarly 7 counts to 0. So in binary 111 to 000.

Last step is filling up Flip Flop inputs. If you use any other Flip Flops the above steps are always required. Just replace J-K latch here with any other latch and use excitation table to complete the state table.

Jc and Kc should be filled only based on present state of C and the next state of C. Similarly for others.

For example, 2 moves to 4. So,

Present -> Next
C B A -> C B A
0 1 0 -> 1 0 0

Here, C’s present state is 0 and next state is 1. So based on J-K excitation table the value will be 1 X.

#### State Table Not Showing Don’t Care Conditions:

##### Flip Flop Inputs
C B A C B A JC KC JB KB JA KA
0 0 0 0 1 0 0 x 1 x 0 x
0 1 0 1 0 0 1 x x 1 0 x
1 0 0 1 0 1 x 0 0 x 1 x
1 0 1 1 1 1 x 0 1 x x 0
1 1 1 0 0 0 x 0 x 1 x 1

#### How to Interpret the Table Above to Generate K Map:

Since this has only three bits. Create a three variable K-Maps. There will be a total of 6 K-Maps since there is two inputs per latch.

Also here 1, 3, 6 are don’t care, so fill these with x. Next 0, 2, 4, 5, 7 these positions are empty in k map. Fill in these position with values from the columns.

#### Karnaugh Map Using Table For Unused Don’t Care Conditions:

Here I have shown the table for don’t care terms for unused states transition to next states. For using specific state transition from unused states set the value from the table above in appropriate place and get the equation. From that equation create the logic diagram.

#### How to Connect the latches from K Map equations:

Here each of the latches are given a name A, B, C. Each of the latches represents a bit. Where C is the Most significant bit (MSB) and A is the least significant bit (LSB). The input of J-K latch for A are JA and KA. Similarly for others.

The next states depends on current state. The output is on the right side. What ever the value of the output on the top output is the bottom one is the prime (opposite) of it.

From the K Map set connections on the left side ( input ) to right side ( output ). This is assuming that the Flip Flop is positioned like shown in the diagram below. Although This may not always be the case.

#### Logic Diagram From the above Karnaugh Map Using Don’t Care For 1, 3, 6 states:

Here I’ve drawn the logic diagram in logisim. If you draw by hand it hand the design will be the same just replace the button with a clock.

Make sure input of KB is always 1. Because that’s the equation for KB in Karnaugh Map.

#### How to check if the Arbitrary counter is working:

Select the hand tool below File menu. Also make sure input of JB is set to 1. Now click on the button to give clock pulse.

## 7 Segment Decoder Implementation, Truth Table, Logisim Diagram

7 Segment Decoder Implementation, Truth Table, Logisim Diagram:

### 7 Segment Decoder:

For reference check this Wikipedia link.

### Pictures:

(Wikipedia CC BY-SA 2.5)

### Explanation:

Before we start implementing we first need to check if it is common anode or common cathode. If it is common anode then 3rd pin in both top and bottom are VCC. But if it is we should connect 3rd pin in both top and bottom to ground.

Pins:

show top pins then bottom pins ( Dot side is down ).

        Pin1   Pin2   Pin3   Pin4   Pin5
Top:     g      f    vcc/GND   a     b
Bottom:  e      d    vcc/GND   c     dp


### Truth Table:

From here we can get minimized expressions for a, b, c, d, e, f, g using K-MAP. Here we only need value 0 though 9 rest are don’t care terms. Using those don’t care terms we will try to maximum ones first.

### K-Map (Karnaugh map) for ‘a’:

We can follow similar procedure for the rest. K map for ‘a’ can be created by taking the ‘a’ column from the table above and setting the value 0 / 1 to corresponding location in the table. For example to display 0 ( 0000 )  ‘a’ is always 1. Similarly to display 1 ‘a’ is always 0. For value ( 10 – 16 ) we don’t care about them so they are used as don’t care term in k map.

## Boolean Algebra Proofs Postulates and Theorems (Part 2)

Boolean Algebra Postulates and Theorems (Part 2):

x + y = y + x;
x .  y  = y . x;

#### Associative Law:

x + (y + z) = (x + y) + z;
x .  (y .  z) = (x  . y) .  z;

#### Distributive law:

x . (y + z) = x  .  y  + x  .  z;
x + (y . z) = (x + y) . (x + z);

#### De Morgan’s Law:

(x + y)’ = x’ .  y’;
(x .  y)’ = x’ + y’;

x + x  .  y = x;
x . (x + y) = x;

#### Absorption Law Proof:

x + x.y = x
L.H.S =>
= x.(1 + y)   [Distributive Law]
= x.1         [We know, x + 1 = x]
= x           [We know, x . 1 = x]
= R.H.S


## Digital Logic AND Gate with C Bitwise Operations

#### Digital Logic AND Gate with C Bitwise Operations:

##### AND Logic:

A, B is input, Q is output,

A . B = Q  /* AND is represented by dot ( . ) */

AND Truth Table,

A  B     Q (A . B)
==========
0  0     0
0  1     0
1  0     0
1  1     1


##### C Code:
In C, C++ AND bit wise AND can be performed using &( Ampersand )

Don’t confuse single logical AND ( Double Ampersand && ) with bitwise AND ( Single Ampersand & ).

printf("%d\n", 5 & 6 );    /* Output 4  */
printf("%d\n", 8 & 4 );    /* Output 0  */
printf("%d\n", 54 & 29);   /* Output 20 */


##### Code Explanation:

Bit wise AND takes two binary digits of same length and performs AND operation on corresponding bits of first and second number. If both bits are 1 then result is 1, otherwise result is 0. Use the table given above.

5 & 6 = 4,

0101 # 5        /* 0 + 4 + 0 + 1 = 5 */
0110 # 6        /* 0 + 4 + 2 + 0 = 6 */
=========
0100 # 4        /* 0 + 4 + 0 + 0 = 4 */


8 & 4 = 0,

1000 # 8        /* 8 + 0 + 0 + 0 = 8 */
0100 # 4        /* 0 + 4 + 0 + 0 = 4 */
=========
0000 # 0        /* 0 + 0 + 0 + 0 = 0 */


54 & 29 = 20,

0011 0110 # 54  /* 0 + 0 + 32 + 16 + 0 + 4 + 2 + 0 = 54 */
0001 1101 # 29  /* 0 + 0 +  0 + 16 + 8 + 4 + 0 + 1 = 29 */
==============
0001 0100 # 20  /* 0 + 0 +  0 + 16 + 0 + 4 + 0 + 0 = 20 */


## Decimal Number Representation in Binary ( Binary to Decimal Explanation )

##### Decimal Number Representation in Binary ( Binary to Decimal Explanation ):

Binary means base-2 number system. There are only two symbols 0 ( Zero ) and 1 ( One ). Each Binary Digit is called bit. Calculating decimal equivalent of binary number is easy. Index is always from bit Count Minus One to Zero.

We start raising two to the power 0 from the right most bit and increment for each left bit. Another way is we start from right raising two to the power of bit length – 1 and decrement for every right bit.

Our base is two. Whenever we find a 1 in binary number we raise its index to power of 2 and sum all those numbers. See example below,

5 in 3 bit binary is, 101

0  1  0  1
23 22 21 20
0  4  0  1   /* summing these gives us 5 */


54 in 6 bit binary is, 110110

1   1   0   1  1  0
25  24  23  22  21 20
32  16  0   4  2  0   /* summing these gives 54 */


###### Extras,

Bit pattern count = 2bit
8 bit = 1 Byte

Byte is represented by Capital B while bit is represented by small b.
MB = Megabyte
Mb = Megabit

## Basic Gate IC’s

#### Basic IC’s ( Integrated Circuits ):

Basic Integrated Circuits: